The present invention relates generally to the manufacturing and testing of integrated circuit chips. Specifically, a method and apparatus are provided for testing an integrated circuit chip having more signal pins than the number of available channels on a integrated circuit chip tester.
Integrated circuit chips customarily undergo exhaustive testing during the manufacture process prior to encapsulation in a package or use of the package on a circuit board in order to ensure reliable operation of the chip. The chip die undergoes functional and parametric testing in at least two different stages of the manufacturing process. At one stage, the semiconductor wafer containing multiple chip dice is probed by a probe tester that tests each of the dice individually. At another stage, after an individual chip die has been encapsulated in a package, a package tester programmed to exercise the functions of the chip couples the tester's channels to signal pins of the integrated circuit chip package. In either case, the device tester applies excitations to and receives responses from the chip being tested under control of the tester in order to provide test results. This procedure generally can be completed in only one testing step since the number of available tester channels is usually greater than or equal to the number of signal pins on an integrated circuit chip die or package to be tested. The tester can thoroughly exercise and test all of the chip's functions in one step since each of the signal pins on the chip package is coupled to a tester channel. However, when testing devices with very high pin counts, the chip die or package might have more signal pins than the number of tester channels, making it impossible to test the chip in only one testing step. Thus, a method and apparatus are needed to efficiently test an integrated circuit chip having more signal pins than the number of available channels on a chip tester.